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NCP5381A 2/3/4 Phase Buck Controller for VR10 and VR11 Pentium IV Processor Applications
The NCP5381A is a two-, three-, or four-phase buck controller which combines differential voltage and current sensing, and adaptive voltage positioning to power Intel's most demanding Pentium (R) IV Processors and low voltage, high current power supplies. Dual-edge pulse-width modulation (PWM) combined with inductor current sensing reduces system cost by providing the fastest initial response to transient loads thereby requiring less bulk and ceramic output capacitors to satisfy transient load-line requirements. A high performance operational error amplifier is provided, which allows easy compensation of the system. The proprietary method of Dynamic Reference Injection (Patent Pending) makes the error amplifier compensation virtually independent of the system response to VID changes, eliminating the need for tradeoffs between load transients and Dynamic VID performance.
Features http://onsemi.com MARKING DIAGRAM
1 40
1
40 PIN QFN, 7x7 MN SUFFIX CASE 488AG
NCP5381A AWLYYWWG
* * * * * * * * * * * * * * * * * * * * * * * * * * *
Meets Intel's VR 10.0, 10.1, 10.2, and 11.0 Specifications Dual-Edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifier Supports both VR11 and Legacy VR10 Soft-Start Modes Dynamic Reference Injection (Patent Pending) 8-Bit DAC per Intel's VR11 Specifications DAC Range from 0.5 V to 1.6 V "0.5% System Voltage Accuracy Remote Temperature Sensing per VR11 2, 3, or 4-Phase Operation True Differential Remote Voltage Sensing Amplifier Phase-to-Phase Current Balancing "Lossless" Differential Inductor Current Sensing Differential Current Sense Amplifiers for each Phase Adaptive Voltage Positioning (AVP) Fixed No-Load Voltage Positioning at -19 mV Frequency Range: 100 kHz-1.0 MHz Latched Overvoltage Protection (OVP) Threshold Sensitive Enable Pin for VTT Sensing Power Good Output with Internal Delays Programmable Soft-Start Time Operates from 12 V This is a Pb-Free Device* Pentium IV Processors VRM Modules Graphics Cards Low Voltage, High Current Power Supplies
NCP5381A = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package *Pin 41 is the thermal pad on the bottom of the device.
ORDERING INFORMATION
Device NCP5381AMNR2G Package Shipping
QFN-40 2500 / Tape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Applications
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
August, 2006 - Rev. 4
1
Publication Order Number: NCP5381A/D
NCP5381A
PIN CONNECTIONS
40 39 38 37 36 35 34 33 32 G3 31 G2
VR_HOT
DGND
NTC
VR_FAN
VCC
1 2 3 4 5 6 7 8 9 10
VR_RDY
VREF
G4
EN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
G1 DRVON CS4 CS4N
30 29 28 27 26 25 24 23 22 21
NCP5381A
CS3 CS3N CS2 CS2N CS1 DIFFOUT COMP
ROSC
AGND
11
12
13
14
15
16
17
18
19
(Top View)
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2
20
VDRP
VR10/11 SS
CS1N
ILIM
VFB
VS+
VS-
NCP5381A
VR10/11 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 SS VREF NTC VR_FAN + - DAC + VS- VS+ DIFFOUT 1.3 V VFB COMP VDRP + - Error Amp Droop Amplifier 1.3 V CS1 CS1N CS2 CS2N CS3 CS3N CS4 CS4N + -
Gain = 6 + -
NCP5381A VR10/11 DAC
NTC
VR_HOT
- + Diff Amp Fault
-
DGND
+ - + - + - + -
4OFF OVER Fault
ENB
G1
+ -
Gain = 6
ENB
G2
Gain = 6
+ - + -
ENB
G3
ENB
G4
Gain = 6
Oscillator ROSC DIFFOUT 1.3 V + - Current Limit EN VCC AGND 9.0 V + - UVLO
ILIM
Fault Logic 3 Phase Detect and Monitor Circuits
DRVON
VR_RDY
Figure 1. Simplified Block Diagram http://onsemi.com
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NCP5381A
+12 V VTT 680 W PULLUPS RVCC 12 V_FILTER D1 BAT54HT1 C3 NCP3418B 36 U20 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_HOT VR_FAN 2 3 4 5 6 7 8 9 10 1 37 40 39 16 15 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VR10/11 EN VR_RDY VR_HOT VR_FAN VS- VS+ VREF NTC DGND AGND 14 34 38 RNTC1 C1 NTD85N02RT4 RNTC2 35 RT1 4 3 2 VCC OD IN BST DRVH SW DRVL PGND 1 8 7 5 6 R2 C2 RS1 NTD60N02RT4 L1 12 V_FILTER C4 CVCC1
30 G1 22 CS1 CS1N 21 G2 31 12 V_FILTER 12 V_FILTER
CS1
24 CS2 CS2N 23 G3 CS3 32 4 3 2 VCC OD IN BST DRVH SW DRVL PGND 1 8 7 5 6
RISO1 RT2 CFB1 RFB
RISO2
26
NCP5381A CS3N 25
G4 33
RFB1
17 19
DIFFOUT VFB
28 CS4 CS4N 27 12 V_FILTER 12 V_FILTER 29
RDRP 20 CD1 RD1 18 CF RF COMP ILIM 13 CH RLIM1 CSS ROSC SS 12 11 VDRP DRVON
4 3 2
VCC OD IN
BST DRVH SW DRVL PGND
1 8 7 5 6
RLIM2
12 V_FILTER
12 V_FILTER
4 3 2
VCC OD IN
BST DRVH SW DRVL PGND
1 8 7 5 6
RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU GND
Figure 2. Application Schematic for Four Phases http://onsemi.com
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NCP5381A
+12 V VTT 680 W PULLUPS RVCC 12 V_FILTER D1 BAT54HT1 C3 NCP3418B 35 RT1 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VR10/11 EN VR_RDY VR_HOT VR_FAN VS- VS+ VREF NTC DGND AGND 14 34 RNTC1 38 RNTC2 4 3 2 VCC OD IN BST DRVH SW DRVL PGND 1 8 7 5 6 R2 C2 CS1 RS1 NTD60N02RT4 L1 12 V_FILTER C4 CVCC1 36 U1 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_HOT VR_FAN 2 3 4 5 6 7 8 9 10 1 37 40 39 16 15
C1
NTD85N02RT4
30 G1 22 CS1 CS1N 21 G2 31 12 V_FILTER 12 V_FILTER
24 CS2 CS2N 23 G3 CS3 32 4 3 2 VCC OD IN BST DRVH SW DRVL PGND 1 8 7 5 6
RISO1
RT2
RISO2
26
NCP5381A CS3N 25
33
CFB1 RFB
RFB1 17 19 DIFFOUT VFB
G4
28 CS4 CS4N 27 12 V_FILTER 12 V_FILTER 29
RDRP 20 CD1 RD1 18 CF RF COMP ILIM 13 CH RLIM1 ROSC SS 12 11 VDRP DRVON
4 3 CSS 2
VCC OD IN
BST DRVH SW DRVL PGND
1 8 7 5 6
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS
VCCP + VSSP CPU GND
Figure 3. Application Schematic for Three Phases
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NCP5381A
+12 V VTT 680 W PULLUPS RVCC 12 V_FILTER D1 BAT54HT1 C3 NCP3418B 35 RT1 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VR10/11 EN VR_RDY VR_HOT VR_FAN VS- VS+ VREF NTC DGND AGND 14 34 38 RNTC1 RNTC2 4 3 2 C1 VCC OD IN BST DRVH SW DRVL PGND 1 8 7 5 6 R2 RS1 NTD85N02RT4 C2 CS1 NTD60N02RT4 L1 12 V_FILTER C4
CVCC1 36
U21 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_HOT VR_FAN 2 3 4 5 6 7 8 9 10 1 37 40 39 16 15
30 G1 22 CS1 CS1N 21 G2 31 12 V_FILTER 12 V_FILTER
24 CS2 CS2N 23 G3 CS3 32 4 3 2 VCC OD IN BST DRVH SW DRVL PGND 1 8 7 5 6
RISO1
RT2
RISO2
26
NCP5381A CS3N 25
33
CFB1 RFB
RFB1
17 19
DIFFOUT VFB
G4
28 CS4 CS4N 27 29
RDRP 20 CD1 RD1 18 CF RF COMP ILIM 13 CH RLIM1 CSS ROSC SS 12 11 VDRP DRVON
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU GND
Figure 4. Application Schematic for Two Phases
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NCP5381A
PIN DESCRIPTIONS
Pin No. 1 Symbol EN Description Pull this pin high to enable controller. Pull this pin low to disable controller. Either an open-collector output (with a pull-up resistor) or a logic gate (CMOS or totem-pole output) may be used to drive this pin. A Low to High transition on this pin will initiate a soft start. If the Enable function is not required, this pin should be tied directly to VREF. Voltage ID DAC inputs. VR select bit. Connect this pin to VTT (1.25 V) to select the VR11 DAC table. Ground this pin to select the VR10 DAC table with VR11 type startup. Connect this pin to VREF (4 V) to select VR10 DAC table with legacy VR10 type startup. A capacitor from this pin to ground programs the soft-start time. A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies a regulated 2.0 V which may be used with a voltage divider to the ILIM pin to set the over current shutdown threshold as shown in the Applications Schematics. Over current shutdown threshold. To program the shutdown threshold, connect this pin to the ROSC pin via a resistor divider as shown in the Applications Schematics. To disable the over current feature connect this pin directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin - do not connect this pin to any externally generated voltages. Power supply return for the analog circuits that control output voltage. Non-inverting input to the internal differential remote VCORE sense amplifier. Inverting input to the internal differential remote VCORE sense amplifier. Output of the differential remote sense amplifier. Output of the error amplifier. Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and the amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP) during load. Current signal output for Adaptive Voltage Positioning (AVP). The voltage of this pin minus 1.3 V is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP current into the feedback resistor (RFB) to produce an output voltage droop. Leave this pin open for no AVP. Inverting input to current sense amplifier #x, x = 1, 2, 3, 4. Non-inverting input to current sense amplifier #x, x = 1, 2, 3, 4. Gate Driver enable output. This pin produces a logic HIGH to enable gate drivers and a logic LOW to disable gate drivers and has an internal 70 kW to ground. PWM control signal outputs to gate drivers. Voltage reference pin. This pin may be used to implement remote NTC temperature sensing as shown in the Applications Schematic. Power supply return for the digital circuits. Connect to AGND. Power for the internal control circuits. Voltage Regulator Ready (PowerGood) output. Open drain type output with internal delays that will transition High when VCORE is higher than 300 mV below DAC, Low when VCORE is lower than 380 mV below DAC, and Low when VCORE is higher than DAC+185 mV. This output is latched Low if VCORE exceeds DAC+185 mV until VCC is removed. Remote temperature sense connection. Connect an NTC thermistor from this pin to GND and a resistor from this pin to VREF. As the NTC's temperature increases the voltage on this pin will decrease. Open drain type of output that will be low impedance when the voltage at the NTC pin is above 1.416 V. This pin will transition to a high impedance state when the voltage at the NTC pin decreases below 1.176 V. Open drain type of output that will be low impedance when the voltage at the NTC pin is above 1.086 V. This pin will transition to a high impedance state when the voltage at the NTC pin decreases below 0.846 V. Copper pad on the bottom of the IC for heatsinking. This pin should be connected to the ground plane under the IC.
2-9 10
VID0-VID7 VR10/VR11
11 12
SS ROSC
13
ILIM
14 15 16 17 18 19
AGND VS+ VS- DIFFOUT COMP VFB
20
VDRP
21, 23, 25, 27 22, 24, 26, 28 29 30 - 33 34 35 36 37
CSxN CSx DRVON G1 - G4 VREF DGND VCC VR_RDY
38 39 40 41
NTC VR_FAN VR_HOT THPAD
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NCP5381A
MAXIMUM RATINGS
Rating Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature Soldering, Reflow (60 to 120 seconds minimum above 237C): Thermal Resistance, Junction-to-Ambient (RJA) on a thermally conductive PCB in free air JEDEC Moisture Sensitivity Level Maximum Voltage - VCC pin with respect to AGND Maximum Voltage - all other pins with respect to AGND Minimum Voltage - all pins with respect to AGND Maximum Current into pins: COMP, VDRP, DIFFOUT, VREF Maximum Current into pins: VR_RDY, G1, G2, G3, G4, SS, VR_FAN, VR_HOT, DRVON Maximum Current out of pins: COMP, VDRP, DIFFOUT, ROSC, VREF Maximum Current out of pins: G1, G2, G3, G4 Value 0 to 70 0 to 85 -55 to 150 260 83 3 15 5.5 -0.3 3.0 20 3.0 20 Unit C C C C C/W MSL V V V mA mA mA mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: ESD Sensitive Device.
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 85C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
Error Amplifier
Input Bias Current Inverting Input Voltage Input Offset Voltage (Note 1) Open Loop DC Gain (Note 1) Open Loop Unity Gain Bandwidth (Note 1) Open Loop Phase Margin (Note 1) Slew Rate (Note 1) CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND DVin = 100 mV, G = -1.0 V/V, 1.2 V < Vout < 2.2 V, CL = 60 pF, DC Load = 125 mA ISOURCE = 1.0 mA ISINK = 1.0 mA Vout = 3.0 V Vout = 1.0 V 1.0 kW between VFB and COMP Pins -200 - -1.0 - - - - -50 1.3 - 78 15 65 5.0 -10 - 1.0 - - - - nA V mV dB MHz deg V/ms
Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 1) Output Sink Current (Note 1)
3.0 - - -
3.3 0.9 2.0 2.0
- 1.0 - -
V V mA mA
Remote Sense Differential Amplifier
VS+ Input Resistance (Note 1) VS+ Input Open Circuit Voltage (Note 1) VS- Input Resistance (Note 1) VS- Input Open Circuit Voltage (Note 1) DRVON = High DRVON = Low DRVON = High DRVON = Low VS+ = DAC Voltage DRVON = High DRVON = High VS+ = DAC Voltage - - - - - 17 0.5 0.67 0.05 10 = 0.333*DA C + 0.433 -0.3 -1.0 CL = 80 pF to GND, RL = 10 kW to GND IDIFFOUT = 100 mA DVin = 1.0 V, DVout = 1.0 V to 2.0 V, CL = 80 pF to GND, Load = 125 mA ISOURCE = 1.0 mA ISINK = 1.0 mA Vout = 2.1 V Vout = 1.0 V - 0.982 - - - 12 1.000 10 3.0 1.0 - 1.018 - - - - - - kW V kW V
Input Voltage Range Input Offset Voltage (Note 1) -3dB Bandwidth (Note 1) DC Gain Slew Rate (Note 1)
V mV MHz V/V V/ms
Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 1) Output Sink Current (Note 1)
3.0 - - -
- - 25 1.4
- 0.5 - -
V V mA mA
1. Guaranteed by design. Not tested in production.
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 85C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
VDRP Adaptive Voltage Positioning Amplifier
Current Sense Input to VDRP Gain Current Sense Input to VDRP Output -3dB Bandwidth (Note 1) Current Sense Input to VDRP Output Slew Rate (Note 1) -60 mV < (CSx-CSxN) < +60 mV, TA = 25C CL = 330 pF to GND, RL = 10 kW to GND DV(CSx-CSxN) = 25 mV (all phases), 1.3 V < Vout < 1.9 V, CL = 330 pF to GND, Load = 400 mA CSx - CSxN = 0, CSx =1.0 V CSx - CSxN = 0.12 V (all phases), ISOURCE = 1.0 mA CSx - CSxN = -0.12 V (all phases), ISINK = 1.0 mA VDRP = 2.9 V VDRP = 1.0 V 5.7 - - 6.0 7.2 3.7 6.3 - - V/V MHz V/ms
Current Summing Amp Output Offset Voltage Maximum VDRP Output Voltage
-15 3.02
- -
+15 -
mV V
Minimum VDRP Output Voltage
-
-
0.5
V
Output Source Current (Note 1) Output Sink Current (Note 1)
- -
9.0 2.0
- -
mA mA
Current Sense Amplifiers
Input Bias Current Common Mode Input Voltage Range (Note 1) Differential Mode Input Voltage Range Input Offset Voltage (Note 1) Current Sense Input to PWM Comparator Input Gain CSx = CSxN = 1.0 V 0 mV < (CSx-CSxN) < 25 mV TA = 25C CSx = CSxN = 1.4 V -200 -0.3 -120 -3.0 5.7 -100 - - - 6.0 - 2.0 120 3.0 6.3 nA V mV mV V/V
Oscillator
Switching Frequency Range (Note 1) Switching Frequency Accuracy (Note 1) Switching Frequency Accuracy Switching Frequency Accuracy Switching Frequency Accuracy Switching Frequency Accuracy (Note 1) Switching Frequency Accuracy Switching Frequency Accuracy Switching Frequency Accuracy ROSC Output Voltage ROSC Output Voltage (Note 1) ROSC = 100 kW, 2 or 4-phase ROSC = 49.9 kW, 2 or 4-phase ROSC = 24.9 kW, 2 or 4-phase ROSC = 10 kW, 2 or 4-phase ROSC = 100 kW, 3-phase ROSC = 49.9 kW, 3-phase ROSC = 24.9 kW, 3-phase ROSC = 10 kW, 3-phase 10 kW < ROSC < 49.9 kW 49.9 kW < ROSC < 100 kW 100 93.6 184.5 360 829 90 178.2 351 818 1.92 - - 104 205 400 921 100 198 390 909 2.00 2.00 1000 114.4 225.5 440 1013 110 217.8 429 1000 2.08 - kHz kHz kHz kHz kHz kHz kHz kHz kHz V V
1. Guaranteed by design. Not tested in production.
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 85C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
Modulators (PWM Comparators)
Minimum Pulse Width Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle Minimum PWM Linear Duty Cycle (Note 1) PWM Comparator Offset Mismatch (Note 1) Phase Angle Error Propagation Delay (Note 1) Propagation Delay (Note 1) COMP voltage when the PWM outputs remain LO COMP voltage when the PWM outputs remain HI FS = 400 kHz Between any 2 phases, FS = 400 kHz Between adjacent phases, FS = 400 kHz Ramp/Comp crossing to Gx high Ramp/Comp crossing to Gx low Fs = 400 kHz - - - - - - -15 - - 30 1.0 1.2 2.3 90 - - 20 20 40 - - - - 40 15 - - ns V V V % mV ns ns
PWM Outputs
Output High Voltage Output Low Voltage Rise Time Fall Time Output Impedance - LO State G4 Gate Pin Source Current during Phase Detect Phase Detection Period G4 Phase Detect Threshold Resistance Sourcing 500 mA Sinking 500 mA CL = 20 pF, DVo = 0.3 to 2.0 V CL = 20 pF, DVo = Vmax to 0.7 V Resistance to GND (Gx = LO) 3.3 - - - - - - - 4.0 25 10 10 50 70 50 - 4.7 100 - - - - - 1.0 V mV ns ns W mA ms kW
Gate Driver Enable (DRVON)
Output High Voltage Output Low Voltage Rise Time Fall Time Internal Pulldown Resistance Sourcing 500 mA Sinking 500 mA CL (PCB) = 20 pF, DVo = 10% to 90% CL (PCB) = 20 pF, DVo = 10% to 90% VCC < UVLO Threshold 4.0 - - - - 5.3 50 25 25 70 5.5 200 - - 140 V mV ns ns kW
1. Guaranteed by design. Not tested in production.
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 85C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
VR_RDY (Power Good) Output
Saturation Voltage Rise Time ISINK = 10 mA External pullup of 1.0 kW to 1.25 V, CLOAD = 20 pF, DVo = 10% to 90% External VR_RDY pullup resistor of 2.0 kW to 5.0 V, tR_VCC 3 x tR_5V, 100 ms tR_VCC 20 ms High - Output Leakage Current Upper Threshold Voltage Rising Delay Falling Delay VR_RDY = 5.5 V via 1.0 K VCORE increasing, DAC = 1.3 V VCORE increasing VCORE decreasing - - 0.3 - - 300 1.40 5.0 1.0 - 2.0 - mA mV below DAC ms ms - - - - 0.4 150 V ns
Output Voltage at Power-up (Note 1)
-
-
1.0
V
VR_FAN AND VR_HOT
NTC Pin Bias Current VR_FAN Upper Voltage Threshold VR_FAN Lower Voltage Threshold VR_FAN Hysteresis VR_FAN Output Voltage at Powerup (Note 1) External Pullup resistor of 2.0 kW to 5.0 V, tR_VCC 3 x tR_5V, 100 ms tR_VCC 20 ms VR_FAN Output Saturation Voltage VR_FAN Output Leakage Current VR_HOT Upper Voltage Threshold VR_HOT Lower Voltage Threshold VR_HOT Hysteresis VR_HOT Output Voltage at Powerup (Note 1) External Pullup resistor of 2.0 kW to 5.0 V, tR_VCC 3 x tR_5V, 100 ms tR_VCC 20 ms VR_HOT Saturation Output Voltage VR_HOT Output Leakage Current ISINK = 4.0 mA High Impedance State, VR_HOT = 5.0 V - - - - 0.3 1.0 V mA ISINK = 4.0 mA High Impedance State, VR_FAN = 5.0 V Fraction of VREF voltage above which VR_HOT output pulls low Fraction of VREF voltage below which VR_HOT output is open - - 0.2732 0.2107 210 - - - 0.2815 0.2190 240 - 0.3 1.0 0.2897 0.2272 270 1.0 mV V V mA 0 V < NTC < 5.0 V Fraction of VREF voltage above which VR_FAN output pulls low Fraction of VREF voltage below which VR_FAN output is open -1.0 0.3518 0.2892 210 - - 0.3625 0.3025 240 - 1.0 0.3737 0.3112 270 1.0 mV V mA
1. Guaranteed by design. Not tested in production.
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 85C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
Soft-Start
SS Pin Source Current SS Pin Source Current Soft-Start Ramp Time SS Pin Discharge Voltage Soft-Start Discharge Time ENABLE = HI, VSS PIN < 1.1 V ENABLE = HI, VSS PIN > 1.15 V, VR11 SS mode only CSS = 0.01 mF, DRVON = HI to VSS PIN = 1.1 V ENABLE = LO From ENABLE = LO to VSS PIN < max Discharge Voltage, CSS = 0.01 mF - 125 1.5 - - 5.0 - 2.2 - 5.0 - - 3.0 50 - mA mA ms mV ms
VR11 VBOOT Threshold Voltage VR11 Dwell Time at VBOOT (Note 1)
- 50
1.081 225
- 900
V ms
Enable Input
Enable High Input Leakage Current Upper Threshold Lower Threshold Total Hysteresis Enable Delay Time Disable Delay Time EN = 3.0 V VUPPER VLOWER VUPPER - VLOWER Enable transitioning HI to start of SS voltage rise Enable transitioning Low to DRVON = Low - 0.80 0.67 70 0.5 - - 0.85 0.75 100 1.5 - 10 0.90 0.83 130 3.0 200 mA V V mV ms ns
Current Limit
Current Sense Inputs to ILIM Gain (Note 1) ILIM Pin Input Bias Current ILIM Pin Working Voltage Range (Note 1) ILIM Input Offset Voltage (Note 1) 20 mV < (CSx-CSxN) < 60 mV TA = 25C (all CS channels together) VILIM = 2.0 V 5.7 6.0 6.3 V/V
- 0.3 -50
0.1 - -
1.0 2.0 50
mA V mV
Overvoltage Protection
Overvoltage Threshold (Note 1) DAC+160 DAC+180 DAC+200 mV
Undervoltage Protection
UVLO Start Threshold UVLO Stop Threshold UVLO Hysteresis 8.2 7.2 - 9.0 8.0 1.0 9.5 8.5 - V V V
VID Inputs
Upper Threshold Lower Threshold Input Bias Current Delay before Latching VID Change (VID De-Skewing) VUPPER VLOWER VVIDX = 1.25 V Measured from the 1st edge of a VID change - 400 - 400 - - 100 - 800 - 500 1000 mV mV nA ns
1. Guaranteed by design. Not tested in production.
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 85C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
VR10/VR11 Select
VR10/VR11 DAC Table Threshold VR10 w/ Legacy SS/VR11 Threshold 0.55 2.7 - - 0.775 3.1 V V
Internal DAC Slew Rate Limiter
Positive Slew Rate Limit Negative Slew Rate Limit VID step range of +10mV to +500mV VID step range of -10mV to -500mV - - 7.3 7.3 - - mV/ms mV/ms
Voltage Reference (VREF)
VREF Output Voltage 0 < IVREF < 250 mA 3.92 4.00 4.08 V
Input Supply Current
VCC Operating Current FSW = 400 kHz - 20 - mA
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 85C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
VR10 DAC
System Voltage Accuracy 1.0 V < DAC < 1.6 V 0.8 V < DAC < 1.0 V 0.5 V < DAC < 0.8 V With CS Input DVin = 0 V - - 0.5 5.0 8.0 % mV mV mV
No-Load Offset Voltage from Nominal DAC Specification
-19
VR10 VID Codes
VID4 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID2 100 mV 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID1 50 mV 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID0 25 mV 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID5 12.5 mV 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID6 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal DAC Voltage (V) 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500
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NCP5381A
VR10 VID Codes
VID4 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID2 100 mV 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID1 50 mV 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID0 25 mV 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID5 12.5 mV 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 OFF OFF
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NCP5381A
VR10 VID Codes
VID4 400 mV 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 200 mV 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 100 mV 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID1 50 mV 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID0 25 mV 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID5 12.5 mV 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) OFF OFF 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125
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NCP5381A
ELECTRICAL CHARACTERISTICS
(0C < TA < 70C; 0C < TJ < 125C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, unless otherwise stated) Parameter Test Conditions Min Typ Max Units
VR 11 DAC
System Voltage Accuracy 1.0 V < DAC < 1.6 V 0.8 V < DAC < 1.0 V 0.5 V < DAC < 0.8 V With CS Input DVin = 0 V - - 0.5 5.0 8.0 % mV mV mV
No-Load Offset Voltage from Nominal DAC Specification
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Table 2: VR11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 HEX
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24
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NCP5381A
Table 2: VR11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 VID3 50 mV 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID2 25 mV 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 12.5 mV 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 HEX
25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
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NCP5381A
Table 2: VR11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID6 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID4 100 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID3 50 mV 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 25 mV 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 12.5 mV 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 HEX
53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80
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NCP5381A
Table 2: VR11 VID Codes
VID7 800 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID2 25 mV 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID1 12.5 mV 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 HEX
81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE
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NCP5381A
Table 2: VR11 VID Codes
VID7 800 mV 1 1 1 1 1 1 VID6 400 mV 0 0 0 0 1 1 VID5 200 mV 1 1 1 1 1 1 VID4 100 mV 0 1 1 1 1 1 VID3 50 mV 1 0 0 0 1 1 VID2 25 mV 1 0 0 0 1 1 VID1 12.5 mV 1 0 0 1 1 1 VID0 6.25 mV 1 0 1 0 0 1 Nominal DAC Voltage (V) 0.51875 0.51250 0.50625 0.50000 OFF OFF OFF HEX
AF B0 B1 B2 FE FF B3 to FD
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NCP5381A
TYPICAL CHARACTERISTICS
ICC, IC QUIESCENT CURRENT (mA) 13.6 13.4 13.2 VCC, UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V) 10
9 VCC Increasing Voltage
13.0 12.8 12.6
8 VCC Decreasing Voltage
0
10
20
30
40
50
60
70
7 0 10 20 30 40 50 60 70 TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 5. IC Quiescent Current vs. Ambient Temperature
Figure 6. VCC Undervoltage Lockout Threshold Voltage vs. Ambient Temperature
0.0198 0.0196 0.0194 DAC OFFSET 0.0192 0.0190 0.0188 0.0186 0.0184 0.0182 0.0180 0.5 0.6 0.7 70C 0.8 0.9 1.0 1.1 VID 1.2 1.3 1.4 1.5 1.6 0C 25C
Figure 7. Typical DAC Voltage Offset vs. Temperature
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NCP5381A
FUNCTIONAL DESCRIPTION
General
The NCP5381A dual edge modulated multiphase PWM controller is specifically designed with the necessary features for a high current VR10 or VR11 CPU power system. The IC consists of the following blocks: Precision Programmable DAC, Differential Remote Voltage Sense Amplifier, High Performance Voltage Error Amplifier, Differential Current Feedback Amplifiers, Precision Oscillator and Triangle Wave Generators, and PWM Comparators. Protection features include Undervoltage Lockout, Soft-Start, Overcurrent Protection, Overvoltage Protection, and Power Good Monitor.
Remote Output Sensing Amplifier (RSA)
shown in the 4-phase Applications Schematic. The Current Sense inputs of unused channels should be connected to ground. The following truth table summarizes the modes of operation:
Gate Output Connections Mode 2-Phase 3-Phase 4-Phase G1 Normal Normal Normal G2 OPEN Normal Normal G3 Normal Normal Normal G4 OPEN GND Normal
These are the only allowable connection schemes to program the modes of operation.
Differential Current Sense Amplifiers
A true differential amplifier allows the NCP5381A to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VS+, and the Vcore ground reference point to VS-. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between Vcore and Vcore ground reference points. The RSA also subtracts the DAC (minus VID offset) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage to allow both positive and negative error voltages.
Precision Programmable DAC
A precision programmable DAC is provided. This DAC has 0.5% accuracy over the entire operating temperature range of the part. The DAC can be programmed to support either VR10 or VR11 specifications. A program selection pin is provided to accomplish this. This pin also sets the startup mode of operation. Connect this pin to 1.25 V to select the VR11 DAC table, and the VR11 startup mode. Connect this pin to ground to select the VR10 DAC table and the VR11 startup mode. Connect this pin to VREF to select the VR10 DAC table and the VR10 startup mode.
High Performance Voltage Error Amplifier
Four differential amplifiers are provided to sense the output current of each phase. The inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1, G2, G3, or G4). If a phase is unused, the differential inputs to that phase's current sense amplifier must be shorted together and connected to VCCP as shown in the 2- and 3-phase Application Schematics. A voltage is generated across the current sense element (such as an inductor or sense resistor) by the current flowing in that phase. The output of the current sense amplifiers are used to control three functions. First, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. In this function, all of the current sense outputs are summed so that the total output current is used for output voltage positioning. Second, the output signal is fed to the current limit circuit. This again is the summed current of all phases in operation. Finally, the individual phase current is connected to the PWM comparator. In this way current balance is accomplished.
Oscillator and Triangle Wave Generator
The error amplifier is designed to provide high slew rate and bandwidth. Although not required when operating as a voltage regulator for VR10 or VR11, a capacitor from COMP to VFB is required for stable unity gain test configurations.
Gate Driver Outputs and 2/3/4 Phase Operation
The part can be configured to run in 2-, 3-, or 4-phase mode. In 2-phase mode, phases 1 and 3 should be used to drive the external gate drivers as shown in the 2-phase Applications Schematic. In 3-phase mode, gate output G4 must be grounded as shown in the 3-phase Applications Schematic. In 4-phase mode all 4 gate outputs are used as
A programmable precision oscillator is provided. The oscillator 's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz/phase to 1.0 MHz/phase. The oscillator generates up to 4 triangle waveforms (symmetrical rising and falling slopes) between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2-, 3-, and 4-phase operation the PWM outputs are separated by 180, 120, and 90 angular degrees, respectively.
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NCP5381A
PWM Comparators with Hysteresis
Four PWM comparators receive the error amplifier output signal at their noninverting input. Each comparator receives one of the triangle waves offset by 1.3 V at it's inverting input. The output of the comparator generates the PWM outputs G1, G2, G3, and G4. During steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by Vout/Vin. During a transient event, both high and low comparator output transitions shift phase to the points where the error amplifier output intersects the down and up ramp of the triangle wave. PROTECTION FEATURES
Undervoltage Lockout
information exceeds the voltage at the ILIM pin. The outputs are immediately disabled, the VR_RDY and DRVON pins are pulled low, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high.
Overvoltage Protection and Power Good Monitor
An undervoltage lockout (UVLO) senses the VCC input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft-start.
Overcurrent Shutdown
An output voltage monitor is incorporated. During normal operation, if the voltage at the DIFFOUT pin exceeds 1.3 V, the VR_RDY pin goes low, the DRVON signal remains high, the PWM outputs are set low. The outputs will remain disabled until the VCC voltage is removed and reapplied. During normal operation, if the output voltage falls more than 300 mV below the DAC setting, the VR_RDY pin will be set low until the output rises.
Soft-Start
A programmable overcurrent function is incorporated within the IC. A comparator and latch makeup this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels - effectively disabling overcurrent shutdown. The comparator noninverting input is the summed current information from the current sense amplifiers. The overcurrent latch is set when the current
2.4 2.2 2.0 1.8 VOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0
The NCP5381A incorporates an externally programmable soft-start. The soft-start circuit works by controlling the ramp-up of the DAC voltage during powerup. The initial soft-start pin voltage is 0 V. The soft-start circuitry clamps the DAC input of the Remote Sense Amplifier to the SS pin voltage until the SS pin voltage exceeds the DAC setting minus VID offset. The soft-start pin is pulled to 0 V if there is an overcurrent shutdown, if the ENABLE pin is low, if VCC is below the UVLO threshold, or if an overvoltage condition exists. There are two possible soft-start modes: Legacy VR10 and VR11. VR10 mode simply ramps Vcore from 0 V directly to the DAC setting at the rate set by the capacitor connected to the SS pin. The VR11 mode ramps Vcore to 1.1 V at the SS capacitor charge rate, pauses at 1.1 V for 170 ms, reads the VID pins to determine the DAC setting, then ramps Vcore to the final DAC setting at the Dynamic VID slew rate of 7.3 mV/ms. Typical VR10 and VR11 soft-start sequences are shown in the following graphs.
VID Setting
Vcore Voltage SS Pin Voltage TIME
Figure 8. Typical VR10 Soft-Start Sequence to Vcore = 1.3 V http://onsemi.com
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NCP5381A
2.4 2.2 2.0 1.8 VOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 TIME Boot Dwell Time NCP5381A Internal Dynamic VID Rate Limit Vcore Voltage SS Pin Voltage Boot Voltage VID Setting
Figure 9. Typical VR11 Soft-Start Sequence to Vcore = 1.3 V
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NCP5381A
APPLICATION INFORMATION The NCP5381A is a high performance multiphase controller optimized to meet the Intel VR11 Specifications. The demo board for the NCP5381A is available by request. It is configured as a four phase solution with decoupling designed to provide a 1.0 mW load line under a 100 A step load. A schematic is available upon request from ON Semiconductor. Startup Procedure The demo board comes with a Socket 775 and requires an Intel dynamic load tool (VTT Tool) available through a third party supplier, Cascade Systems. The web page is http://www.cascadesystems.net/. Start by installing the test tool software. It's best to power the test tool from a separate ATX power supply. The test tool should be set to a valid VID code of 0.5 V or above in-order for the controller to start. Consult the VTT help manual for more detailed instructions.
Startup Sequence
16. Start the second ATX supply by turning it on and setting the PSON DIP switch low. The green VID lights should light up to match the VTT tool VID setting. 17. Set the VR_ENABLE DIP switch up to start the NCP5381A. 18. Check that the output voltage is about 19 mV below the VID setting. Step Load Testing The VTT tool is used to generate the high di/dt step load. Select the dynamic loading option in the VTT test tool software. Set the desired step load size, frequency, duty, and slew rate. See Figures 10 and 11.
1. Make sure the VTT software is installed. 2. Powerup the PC or Laptop do not start the VTT software. 3. Insert the VTT Test Tool adapter into the socket and lock it down. 4. Inset the socket saver pin field into the bottom of the VTT test tool. 5. Carefully line up the tool with the socket in the board and press tool into the board. 6. Connect the scope probe, or DMM to the voltage sense lines on the test tool. When using a scope probe it is best to isolate the scope from the AC ground. Make the ground connection on the scope probe as short as possible. 7. Connect the first ATX supply to the VTT tool. 8. Powerup the first ATX supply to the VTT tool. 9. Start the VTT tool software in VR11 mode with the current limit set to 150 A. 10. Using the VTT tool software, select a VID code that is 0.5 V or above. 11. Connect the second ATX supply to the demo board. 12. Set the VID DIP switches. All the VID switches should be up or open. 13. Set the VR_ENABLE DIP switch down or closed. 14. Set the VR10 DIP switch up or open. 15. Set the VID_SEL switch up or open.
Figure 10. Typical Step Load Response
Figure 11. Typical Load Release Event
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NCP5381A
Dynamic VID Testing The VTT tool provides for VID stepping based on the Intel Requirements. Select the Dynamic VID option. Before enabling the test set the lowest VID to 0.5 V or greater and set the highest VID to a value that is greater than the lowest VID selection, then enable the test. See Figures 12 through 14. Design Methodology An RC input filter is required as shown in the VCC pin to minimize supply noise on the IC. The resistor should be sized such that it does not generate a large voltage drop between the 12 V supply and the IC. See the schematic values.
Understanding Soft-Start Decoupling the VCC Pin on the IC
The controller supports two different startup routines. A legacy VR10 ramp to the initial VID code, or a VR11 Ramp to the 1.1 V VID code, with a pause to capture the VID code then resume ramping to target value based on an internal slew rate limit. See Figures 15 and 16. The controller is designed to regulate to the voltage on the SS pin until it reaches the internal DAC voltage. The soft-start cap sets the initial ramp rate using a typical 5.0 mA current. The typical value to use for the soft-start cap (SS), is typically set to 0.01 mF. This results in a ramp time to 1.1 V of 2.2 ms based on equation 1.
dt Css ^ iss ss dvss 1.1 * V + dvss and i + 5 * mA ss 2.2 * ms dtss Css + 0.01 * mF
Figure 12. 1.6 to 0.5 Dynamic VID Response
(eq. 1)
Figure 13. Dynamic VID Settling Time Rising
Figure 15. VR11 Startup
Figure 14. Dynamic VID Settling Time Falling
Figure 16. VR10 Legacy Startup
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NCP5381A
Programming the Current Limit and the Oscillator Frequency The demo board is set for an operating frequency of approximately 300 kHz. The OSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual values for current limit divider. The series resistors RLIM1 and RLIM2 sink current to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the resistance. The resistance may be estimated by equation 2 or 3 depending on the phase count.
100 90 ROSC (kOhms) 80 70 60 50 40 30 20 10 0 100 200 300 400 500 600 700 800 900 1000 4 Phase Mode 3 Phase Mode
9 32.36 kW ^ 10.14 10 * 1440 300 * k 4 Phase Mode 9 ROSC + 10.14 10 * 1440 Frequency
(eq. 2)
(eq. 3)
3 Phase Mode 9 ROSC + 9.711 10 * 1111 Frequency
Frequency (kHz)
Figure 17. ROSC vs. Phase Frequency
The current limit function is based on the total sensed current of all phases multiplied by a gain of 5.94. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum Calculate the current limit voltage:
VILIMIT ^ 5.94 * IMIN_OCP * DCRTmax )
current limit based on the expected average maximum temperature of the inductor windings.
DCRTmax + DCR25C * (1 ) 0.00393 * C-1 (TTmax-25 * C)) * 0.02
(eq. 4)
Solve for the individual resistors:
V * ROSC RLIM2 + ILIMIT 2*V Final Equation for the Current Limit Threshold ILIMIT(Tinductor) ^
2 * V * RLIM2 RLIM1)RLIM2
DCR50C * Vout * Vin-Vout * (N-1) * Vout L L 2 * Vin * Fs RLIM1 + ROSC-RLIM2
(eq. 5)
(eq. 6)
) 0.02
5.94 * (DCR25C * (1 ) 0.00393 * C-1(TInductor-25 * C)))
*
Vout * Vin-Vout * (N-1) * Vout L 2 * Vin * Fs L
(eq. 7)
The inductors on the demo board have a DCR at 25C of 0.75 mW. Selecting the closest available values of 16.9 kW for RLIM1 and 15.8 kW for RLIM2 yield a nominal operating frequency of 305 kHz and an approximate current limit of 180 A at 100C. The total sensed current can be observed as a scaled voltage at the VDRP pin added to a positive, no-load offset of approximately 1.3 V.
Inductor Selection When using inductor current sensing it is recommended that the inductor does not saturate by more than 10% at maximum load. The inductor also must not go into hard saturation before current limit trips. The demo board includes a four phase output filter using the T50-8 core from Micrometals with 4turns and a DCR target of 0.75 mW @ 25C. Smaller DCR values can be used, however, current sharing accuracy and droop accuracy decrease as DCR decreases. Use the excel spreadsheet for regulation accuracy calculations for a specific value of DCR.
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NCP5381A
Inductor Current Sense Compensation The NCP5381A uses the inductor current sensing method. This method uses an RC filter to cancel out the inductance of the inductor and recover the voltage that is the result of the current flowing through the inductor's
Rsense(T) +
DCR. This is done by matching the RC time constant of the current sense filter to the L/DCR time constant. The first cut approach is to use a 0.47 mF capacitor for C and then solve for R.
(eq. 8)
L 0.47 * mF * DCR25C * (1 ) 0.00393 * C-1 * (T-25 * C))
Figure 18.
inductor temperature final selection of R is best done experimentally on the bench by monitoring the Vdroop pin and performing a step load test on the actual solution. It is desirable to keep the Rsense resistor value below 1.0 k whenever possible by increasing the capacitor values in the inductor compensation network. The bias current flowing out of the current sense pins is approximately 100 nA. This current flows through the current sense resistor and creates an offset at the capacitor which will appear as a load current at the Vdroop pin. A 1.0 k resistor will keep this offset at the droop pin below 2.5 mV. Simple Average PSPICE Model A simple state average model shown in Figure 19 can be used to determine a stable solution and provide insight into the control system.
The demoboard inductor measured 350 nH and 0.75 mW at room temp. The actual value used for Rsense was 953 W which matches the equation for Rsense at approximately 50C. Because the inductor value is a function of load and
E1
+ + --
E 0 GAIN = 6
- + - +
VRamp_min 1.3 V
12 0
1
L
2
DCR (0.85e-3/4)
1
LBRD
2
RBRD 0.75 m CCer (22e-6*18)
(250e-9/4)
- +
Vin 12 0 4
100 p CBulk (560e-6*10) ESRBulk (7e-3/10) 2 ESLBulk (3.5e-9/10)
Voff
1Aac ESRCer 0Adc (1.5e-3/18) 2 ESLCer (1.5e-9/18) 1
+ -
I1 = 10 I2 = 110 TD = 10u TR = 50n TF = 50n PW = 40u PER = 80u
+ -
I2
CH 22 p RF 4.3 k
RDRP 5.11 k
1
0 CF CFB1 1.5 n 680 p RFB1 100
1E3
Unity Gain BW = 15 MHz R6 1k C3 10.6 n 0
RFB
- +
Voff
1k
+ - +
1.3 Voffset
Vout
+ -
VDAC 1.25 V 0
-
0
Figure 19.
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NCP5381A
A complex switching model is available by request which includes a more detailed board parasitic for this demo board. Compensation and Output Filter Design The values shown on the demo board are a good place to start for any similar output filter solution. The dynamic performance can then be adjusted by swapping out various individual components. If the required output filter and switching frequency are significantly different, it's best to use the available PSPICE models to design the compensation and output filter from scratch. The design target for this demo board was 1.0 mW out to 2.0 MHz. The phase switching frequency is currently set to 300 kHz. It can easily be seen that the board impedance of 0.75 mW between the load and the bulk capacitance has a large effect on the output filter. In this case the ten 560 mF bulk capacitors have an ESR of 7.0 mW. Thus the bulk ESR plus the board impedance is 0.7 mW + 0.75 mW or 1.45 mW. The actual output filter impedance does not drop to 1.0 mW until the ceramic breaks in at over 375 kHz. The controller must provide some loop gain slightly less than one out to a frequency in excess 300 kHz. At frequencies below where the bulk capacitance ESR breaks with the bulk capacitance, the DC-DC converter must have sufficiently high gain to control the output impedance completely. Standard Type-3 compensation works well with the NCP5381A. RFB1 should be kept above 50 W for amplifier stability reasons. The goal is to compensate the system such that the resulting gain generates constant output impedance from DC up to the frequency where the ceramic takes over holding the impedance below 1.0 mW. See the example of the locations of the poles and zeros that were set to optimize the model above.
Zout Open Loop Zout Closed Loop Open Loop Gain with Current loop Closed
80 60 40 20 0
Voltage Loop Compensation Gain
1/(2*PI*CFB1*(RFB1+RFB)) 1/(2*PI*CF*RF) RF/RFB 1/(2*PI*(RBRD+ESRBulk)*CBulk)
1/(2*PI*RF*CF) Error Amp Open Loop Gain
RF/RFB1
dB
-20 -40 -60 -80 -100 100
1/(2*PI*SQRT(ESL_Cer*CCer)) 1mOhm 1/(2*PI*CCer*(RBRD+ESRBulk))
1000 10000 100000 1000000 10000000
Frequency
Figure 20.
By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter.
1 1 + 2p * CF * RF 2p * (RBRD ) ESRBulk) * CBulk 1 1 + 2p * CFBI * (RFBI ) RFB) 2p * CCer * (RBRD ) ESRBulk)
(eq. 9)
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NCP5381A
RFB is always set to 1.0 kW and RFB1 is usually set to 100 W for maximum phase boost. The value of RF is typically set to 4.0 kW. Droop Injection and Thermal Compensation The VDRP signal is generated by summing the sensed output currents for each phase and applying a gain of approximately six. VDRP is externally summed into the feedback network by the resistor RDRP. This induces an offset which is proportional to the output current thereby forcing the controlled resistive output impedance. RRDP determines the target output impedance by the basic equation:
Vout + Zout + RFB * DCR * 5.94 RDRP Iout RDRP + RFB * DCR * 5.94 Zout
(eq. 10)
The value of the inductor's DCR varies with temperature according to the following equation 10:
DCRTmax + DCR25C * (1 ) 0.00393 * C-1(TTmax-25 * C))
(eq. 11)
The system can be thermally compensated to cancel this effect out to a great degree by adding an NTC (negative temperature coefficient resistor) in parallel with RFB to reduce the droop gain as the temperature increases. The NTC device is nonlinear. Putting a resistor in series with the
NTC helps make the device appear more linear with temperature. The series resistor is split and inserted on both sides of the NTC to reduce noise injection into the feedback loop. The recommended value for RISO1 and RISO2 is approximately 1.0 kW.
The output impedance varies with inductor temperature by the equation:
Zout(T) + RFB * DCR25C * (1 ) 0.00393 * C-1(T max -25C)) * 5.94 Rdroop
(eq. 12)
By including the NTC RT2 and the series isolation resistors the new equation becomes:
Zout(T) +
RFB * (RISO1)RT2(T))RISO2) RFB)RISO1)RT2(T))RISO2
* DCR25C * (1 ) 0.00393 * C-1(T max -25C)) * 5.94 Rdroop
(eq. 13)
The typical equation of a NTC is based on a curve fit equation 13.
RT2(T) + RT225C * e b 1 *1 298 273 ) T
(eq. 14)
The demo board is populated with a 10 kW NTC with a Beta of 4300. Figure 21 shows the uncompensated and compensated output impedance versus temperature.
VRHOT and VRFAN Thermal monitoring provides two threshold sensitive comparators for thermal monitoring. The circuit consists of two comparators that compare the voltage on the NTC pin to an internal resistor divider connected to VREF. By powering the external temperature sense divider with VREF the tolerance of the VREF voltage is canceled out. The data sheet specifications for the thresholds are shown as ratios with respect to VREF. VR_FAN Upper Threshold Ratio = 0.3625 VR_FAN Lower Threshold Ratio = 0.3025 VR_HOT Upper Threshold Ratio = 0.2815 VR_HOT Lower Threshold Ratio = 0.2190 The following equations can be used to find the temperature trip points.
RT1(T) + RT125C * e b 1 *1 298 273 ) T
(eq. 15)
Figure 21. Uncompensated and Compensated Output Impedance vs. Temperature
RatioNTC(T) :
RNTC2 ) RT1(T) RNTC1 ) RNTC2 ) RT1(T)
(eq. 16)
ON Semiconductor provides an excel spreadsheet to help with the selection of the NTC. The actual selection of the NTC will be effected by the location of the output inductor with respect to the NTC and airflow, and should be verified with an actual system thermal solution.
The demo board contains a 68 K NTC for RT1 with a Beta of 4750. RNTC1 is populated with 15 kW and RNTC2 is populated with a zero ohm resistor. Figure 22 is a plot of equation 15. The horizontal trip thresholds intersect the Ratio NTC curve.
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NCP5381A
further details. The OVP circuit monitors the output of DIFFOUT. If the DIFFOUT signal reaches 180 mV above the nominal 1.3 V offset the OVP will trip. The DIFFOUT signal is the difference between the output voltage and the DAC voltage plus the 1.3 V internal offset. This results in the OVP tracking the DAC voltage even during a dynamic change in the VID setting during operation. Gate Driver and MOSFET Selection ON Semiconductor provides the companion gate driver IC (NCP3418B). The NCP3418B driver is optimized to work with a range of MOSFETs commonly used in CPU applications. The NCP3418B provides special functionality and is required for the high performance dynamic VID operation of the part. Contact your local ON Semiconductor applications engineer for MOSFET recommendations. Board Stack-Up The demo board follows the recommended Intel Stack-up and copper thickness as shown.
Figure 22.
OVP The overvoltage protection threshold is not adjustable. OVP protection is enabled as soon as soft-start begins and is disabled when the part is disabled. When OVP is tripped, the controller commands all four gate drivers to enable their low side MOSFETs, and VR_RDY transitions low. In order to recover from an OVP condition, VCC must fall below the UVLO threshold. See the state diagram for
Figure 23.
Board Layout A complete Allegro ATX and BTX demo board layout file and schematics are available by request at www.onsemi.com and can be viewed using the Allegro Free Physical Viewer 15.x from the Cadence website http://www.cadence.com/.
Close attention should be paid to the routing of the sense traces and control lines that propagate away from the controller IC. Routing should follow the demo board example. For further information or layout review contact ON Semiconductor.
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NCP5381A
PACKAGE DIMENSIONS
40 PIN QFN, 7x7 MN SUFFIX CASE 488AG-01 ISSUE O
A B
D
2X
0.15 C
2X
0.15 C
0.10 C
40 X
0.08 C
SEATING PLANE
40 X 10
L
40 X
Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EEEE EEEE EEEE EEEE
TOP VIEW SIDE VIEW A1 D2
11 20 21 1 40 31 30
PIN ONE LOCATION
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETER. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L k MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 7.00 BSC 5.50 5.70 7.00 BSC 5.50 5.70 0.50 BSC 0.30 0.50 0.20 ---
E
(A3) A C
EXPOSED PAD 40 X
k
E2
b 0.10 C A B 0.05 C
e
BOTTOM VIEW
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NCP5381A/D

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